1. Field of the Invention
This invention relates to a solid-state image sensor, particularly an interline CCD image sensor (i.e., an interline-transfer charge-coupled device image sensor), which can be made compact and which can suppress both blooming and smear.
2. Description of the Prior Art
Although solid-state image sensors are advantageous over pick-up tubes by the compactness, minimization of weight, durability, reliability, etc., of the solid-state image sensors. Moreover, the solid-state image sensors exhibit no burn-in from intense overloads, but they give rise to blooming and smear which do not arise in pick-up tubes. Blooming occurs when excess signal charges in the photodiode overflow into the transfer channel, so that distinct white lines result on the obtained image. While smear takes places when a signal charge generated deep inside the substrate diffuses into the transfer channel, so that indistinct white lines result on the obtained image. Blooming can be eliminated by the use of overflow drains composed of an n.sup.+ -diffusion layer which absorbs excess charges. However, the problem of smear has not yet been solved.
The above-mentioned approach for the elimination of blooming sacrifices photosensitivity and dynamic range of the sensor because the active area is reduced, and accordingly a method for the transfer of the excess charges into the substrate has been proposed by Y. Ishihara et al., "Interline CCD Image Sensor with an Antiblooming Structure", IEEE Transactions on Electron Devices, vol. ED-31, No. 1, January 1984. FIG. 3 shows a unit cell of the interline CCD image sensor described in the above-mentioned article, wherein an n.sup.- -layer 3 constituting a buried channel of the vertical CCD register is formed on a thick p-type layer 13, and an n-type layer 14 constituting a p-n junction photodiode as a photosensitive area is formed on a thin p-type layer 12. Both the thick p-type layer 13 and the thin p-type layer 12 are positioned on an n-type substrate 1. A transfer gate region 7 positioned between the n.sup.- -layer 3 and the n-type layer 14 contains the part of the p-type layer which has not undergone a depletion. This unit cell is electrically isolated from adjacent unit cells by channel stops 6 that are composed of p.sup.+ -layers formed in the surroundings thereof. On the n.sup.- -layer 3 and the transfer gate region 7, a polysilicon electrode 9 is formed, which is an electrode for the vertical CCD register to be driven by pulses .phi.v that are fed to the electrode 9. An A1 film 10 is further formed as a photo-shield on the polysilicon electrode 9.
A reverse bias voltage is applied between the channel stops 6 and the n-type substrate 1, and a complete depletion of the thin p-type layer 12 results.
The pulses .phi.v have three levels, V.sub.H (high), V.sub.M (middle) and V.sub.L (low). When the pulses .phi.v are between the V.sub.M and V.sub.L levels, the n.sup.- -layer 3, which constitutes the vertical CCD register area, is isolated from the n-type layer 14, which constitutes the photosensitive area, by the transfer gate region 7 containing a part of the p-type layer. When the pulses .phi.v are at the highest potential V.sub.H, a signal charge is accumulated in the photosensitive area and transferred from the photosensitive area into the vertical CCD register area through the transfer gate region 7, and the potential of the n-type layer 14, which constitutes the photosensitive area, results in a level equal to the surface potential of the transfer gate region 7. This signal charge is further transferred to a horizontal CCD register (not shown) and read out at a gated charge detector (not shown).
As the photogenerated signal charge is accumulated into the n-type layer 14, the potential of the n-type layer 14 decreases. The excess charges generated in the n-type layer 14 receives intense illumination thereto and are transferred from the n-type layer 14 into the n-type substrate 1 through the thin p-type layer 12 which has been depleted. As a result, blooming is suppressed.
As mentioned above, the conventional image sensor shown in FIG. 3 can suppress blooming, but it still has the following serious problems:
The first problem is that the image sensor cannot be made compact because of the transverse expansion of the thick p-type layer 13. The size of the unit cell cannot be minimized beyond the thickness of the thick p-type layer 13 in the transverse direction because the size of the thick p-type layer 13 is essential to the operation of the unit cell.
The second problem is that smear unavoidably takes place when a signal charge is generated in the non-depleted thick p-type layer 13 and diffuses into the vertical CCD register so that the signal charges are mixed in the vertical CCD register.
In order to eliminate these problems, the inventors of this invention have proposed a solid-state image sensor having a plurality of unit cells in U.S. patent application Ser. No. 770,043, wherein each of the unit cells comprises a photosensitive area and a CCD register for transferring a signal charge generated in said photosensitive area. Both the photosensitive area and the CCD register are disposed on a layer and have different polarities than the charging polarity of the signal charge, which is disposed on a substrate having the same polarity as the signal charge. The photosensitive area has the same polarity as said signal charge, and a suppression of blooming results.
FIG. 4 shows a unit cell of the interline CCD image sensor of the above-mentioned U.S. patent application. This unit cell comprises an n-type substrate 21, a p-type layer 22 formed on the n-type substrate 21, a vertical CCD register composed of a buried channel constituted by an n.sup.- -layer 23 and formed on the p-type layer 22, and a photosensitive area which containing a p-n junction photodiode constituted by an n.sup.- -layer 24 and an n.sup.+ -layer 25.
A transfer gate region 27 containing a part of the p-type layer is positioned between the n.sup.- -layer 23 and the n.sup.+ -layer 25. This unit cell is isolated from adjacent unit cells by channel stops 26 composed of p.sup.+ -layers formed in the surroundings thereof. On the n.sup.- -layer 23 and the transfer gate region 27, the polysilicon electrode 29 functioning as an electrode for the CCD register is driven by pulses .phi.v fed to the electrode 29 and is disposed through an insulating film 28 to the n-type layer and the transfer gate region 27. An A1 film 30 is disposed as a photo-shield on the polysilicon electrode 29.
A reverse bias voltage is applied between the channel stop 26 and the n-type substrate 21. A complete depletion not only in the region of the p-type layer positioned between the substrate 21 and the CCD register, but also in the region of the p-type layer positioned between the substrate 21 and the photodiode area.
The introduction of the pulses .phi.v (having three potential levels, V.sub.H, V.sub.M, and V.sub.L) into the polysilicon electrode of the image sensor of this invention having the above-mentioned structure, the reading out of a signal charge at a gate transfer detector, the control of the transfer of the signal charge into the CCD register, and the control of the accumulation of the signal charge in the photosensitive area are attained in the same manner as for a conventional image sensor. Because the region of the p-type layer positioned below the photodiode area has been depleted, excess charges are generated in the photodiode area that receive intense illumination and are transferred from the photodiode area into the n-type substrate 21 through the n.sup.- -layer 24 and the p-type layer 22 in the same manner as the conventional image sensor in FIG. 3, and a suppression of blooming results. Due to the above-mentioned structure of the image sensor, the region of the p-type layer 22 positioned below the n.sup.- -layer 23 is also depleted and charges are generated deep inside the region that may be transferred into the n-type substrate 21 without the charges diffusing into the CCD register, so that smear can be completely suppressed. Moreover, the transverse expansion of the thick p-type layer that is required in a conventional image sensor is not required in above-mentioned image sensor, so that the image sensor can be made compact.
However, the unit cell shown in FIG. 4 is designed so that the buried channel CCD register and the photosensitive area are disposed on the same p-type well. The following problem is caused as a result: When a reverse bias voltage is applied between the n-type substrate 21 and the p-type well 22 at a low level, electrons are injected from the n-type substrate 21 into the buried channel CCD register 23 through the p-type well 22 formed on the n-type substrate 21 (S. Miyatake et al., "A CCD Imager on Three Types of P-Wells", Jpn. J. Appl. Phys., vol. 24, pp. 574-579, May 1985), and electrons result in being injected into the CCD register. As the impurity concentration of the p-type well 22 becomes lower, the injection voltage of the CCD register becomes higher. Thus, in order to suppress such an injection of electrons, the impurity concentration of the p-type well 22 must be set at a high level. When the impurity concentration of the p-type well 22 is set too high, excess charges are generated in the photosensitive area that receive intense illumination and cannot be transferred from the photosensitive area into the n-type substrate 21 through the p-type well 22, which causes blooming. As mentioned above, the proposed structure of a unit cell of the interline CCD image sensor attains a suppression of smear and a compact structure, but the impurity concentration of the p-type well 22 must be set so that excess charges in the photodiode area overflow into the n-type substrate 21 through the p-type well 22. Therefore, electrons are not injected from the n-type substrate 21 into the buried channel CCD register 23, and the impurity concentration of the p-type well 22 is not limited.